Electrically programmable semiconductor memories, such as EPROMs, EEPROMs and Flash EEPROMs, are organized in a matrix structure wherein the single memory elements are located at the intersection of rows ("word lines") and columns ("bit lines") of the matrix: to access a given memory element, it is necessary to select the word line and bit line at the intersection of which said memory element is located; to this purpose, the memory address bus is divided into row and column address signals, which are decoded independently.
In byte- or word-organized memories, having a data bus comprising respectively eight or sixteen bits, each bit in the data bus is associated with a portion of the memory matrix which comprises a group of said bit lines; each logic configuration of the column address signals causes the simultaneous selection of one bit line in each group. Each group of bit lines is associated with a respective sensing circuitry for reading the information stored in the memory elements which belong to said portion of the memory matrix, and to a programming load circuitry for programming the memory elements connected to said group of bit lines.
It is more and more usual to provide the memory devices with an internal control circuitry to automatize the programming operation; this is especially true for Flash EEPROM devices, which are intended to be programmed on-board directly by a microcontroller and for which it is therefore desirable that the programming operation is performed without keeping the microcontroller busy. Such control circuitry allows the implementation of intelligent programming algorithms, according to which the programming voltages are applied to the selected memory elements only if they are not already in the programmed state, to avoid that the memory elements undergo unnecessary stresses so that the overall life of the device is extended, and on a repeated-pulse basis, with a program verify step after each programming pulse. Said internal control circuitry generally comprises a plurality of control circuits controlling the activation of the programming load circuitry which is associated with each of said groups of bit lines, and a central control circuitry.
It is also known that in the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type arises because, in a semiconductor memory device, the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to avoid that the presence of a limited number of defective memory elements forces the rejection of the entire chip, and therefore to increase the manufacturing process yield, a certain number of additional memory elements are manufactured in the memory matrix. These additional elements are commonly called "redundancy memory elements" and are used as replacement elements for those that, during testing of the memory device, prove defective. Selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry", while the set of redundancy memory elements and circuitry is defined for short as "redundancy."
The redundancy circuitry comprises programmable non-volatile memory registers suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy, both word lines and bit lines of redundancy memory elements are generally provided in the memory matrix; each redundancy word line or bit line is associated with a respective non-volatile memory register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected.
In a known memory matrix architecture, each of said groups of bit lines, i.e., each matrix portion which is associated with one bit in the data bus of the memory device, comprises a set of redundancy bit lines; since in the redundancy circuitry the non-volatile registers associated with the redundancy bit lines only store the logic configuration of the column address signal, the replacement of a defective bit line in one group with a redundancy bit line of the associated set causes such replacement to occur for all those bit lines in the other groups which share with the defective bit line the same column address signal logic configuration, even if they are not defective. This leads to a waste of redundancy resources, and limits the repairability rate of the memory devices.